Draft Proposal

March 24

In the time leading up to turning in the first draft of our proposal, several decisions were made about our project. Some of the most relevant things include:

• Finding the official specification for RISC-V (which later turned out to be out of date)
• Deciding to implement the RV32E base implementation, to reduce the number of parts we need to purchase
• Looking into simulating our design using Verilog before building it
• Identifying the original software in our project as an interface for programming the CPU
• Discussion of what peripherals we could build (Isaac really wants to make a graphics co-processor again, and Daniel wants to make an LED grid)

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Prototype Plan

April 6

We met during the regular class time to figure out what we could build for the prototype demonstration. We landed at a half size (16-bit) ALU, and identified what all that would entail. We aimed to be able to perform each of the arithmetic and logical operations included in the RV32E ISA, which are ADD, SUB, AND, OR, XOR, SLL, SRL, and SRA. We finished with the following diagram:

This diagram includes:

• Discrete components for performing addition, bitwise OR, and bitwise XOR
• A pair of inverting and non-inverting tri-state buffers on both inputs
• Tri-state buffers for every output, which are selected by a decoder
  • Including an inverting buffer on the output of OR, allowing bitwise AND
• A shift unit that was undecided based on difficulty level, which was later downgraded to a microcontroller

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Prototype Construction

April 15, 17, 18, 19

Upon receiving approval for our prototype, Isaac ordered all of the parts we would need. As soon as the parts arrived, we began the tedious task of wiring everything together on breadboards. We made several realizations during this time, including that we had not planned an organized way to connected each of the breadboards. We also had made an error and ordered a decoder that was incompatible with our buffers. We pushed forwards anyways, and were able to finish the prototype without any time to spare, just with more functions than originally intended implemented on the microcontroller.

Below are some images from during the build process:

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Proposal Assignments

April 26

With the impending due date of the final draft of the proposal for this project, we met to make the plans of how we were going to finish the draft and what the rest of the content would be.

The largest decision that was a result of this meeting was splitting our project into stages that help us to use incremental design, and into regions that can be implemented in parallel by each team member.

The hardware stages were decided as:

1. Verilog: A full simulation of the design of our processor
2. Microcontrollers: A cheaper and easier physical build of the processor made out of multiple microprocessors, providing us a functioning processor we can fall back to
3. Discrete Logic: Replace as many functions originally performed by microcontrollers to be performed by TTL chips as we can.

This also involved splitting the processor into a region for each team member, summarized and illustrated as:

• Isaac: Memory and I/O
• Daniel: ALU and Register File
• Alex: Controller and Program Counter

The software was also split into three stages which can implemented in parallel:

• Isaac: Programmer
• Daniel: Compiler
• Alex: Simulator

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Return From Summer

August 24

After an enjoyable summer, we returned to the first week of classes having completed some of the things we planned for the summer, and created a plan for the semester that set out due dates that would keep us moving towards our goal and keep each other accountable.

The main topic of the meeting was the layout of the PCBs, and a timeline for ordering 3 separate revisions to allow for corrections. It was decided that we could split the design into 4 PCBs for:

• Memory and I/O
• Controller
• Register File
• ALU

We drew out these boards and the connections between them, helping us to realize the significant cost that would come from ordering that many shift registers, leading to the decision that the bus wires would be purely visual.

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